1. Field of the Invention
This invention relates generally to the reduction or elimination of alias signals in the outputs of discretely timed circuits. More particularly, it relates to an efficient apparatus and technique for reducing and even eliminating lower alias signals in a frequency domain.
2. Background of Related Art
All discretely timed circuits (i.e., having an input clock signal) have, in the frequency domain, copies of a desired output signal repeated above and below all harmonics of the clock frequency. These signal copies are known as aliases.
Exemplary discretely timed circuits, while by no means exclusive, include such circuits as a digital-to-analog converter (DAC), a switched capacitor filter, and/or a direct digital synthesizer (DDS).
To improve the fidelity of a discrete time signal in a continuous time application, a low pass filter forming an anti-alias filter is conventionally utilized on the output signal to remove undesired frequency components such as the alias signals.
For instance, FIG. 4 shows a block diagram of an exemplary discretely timed circuit, i.e., a DDS 300 forming an oscillator, and including a low pass filter 312 at an output to filter out undesired frequency components forming alias signals. The DDS 300 further includes a frequency register 302.
The frequency register 302 sets the output frequency of the DDS 300, an adder 304, and a phase accumulator 306. The setting in the frequency register 302 is added in the adder 304 each cycle to the feedback line from the phase accumulator 306. The phase accumulator accumulates or stores the output of the adder 304, dropping overflow values.
A look-up table is typically formed to output a desired wave shape. In the disclosed example, the desired output shape is sinusoidal. Thus, the desired look-up table is formed as a xe2x80x9ccosinexe2x80x9d memory, e.g., in Read Only Memory (ROM) 308. Based on the output of the phase accumulator 306, the cosine ROM 308 outputs digital values representing a voltage level of a sinusoidal waveform at the particular point in time. Of course, the cosine ROM 308 contains only discrete values along the desired waveform, but preferably the discrete nature is within the requirements of the particular application.
A digital-to-analog converter (DAC) 310 converts the discrete values output from the cosine ROM 308 into an analog signal, which would otherwise form the output signal from the DDS 300, but for the anti-alias low pass filter 312, which removes alias signals from the output signal.
The phase of the output of the DDS oscillator 300 is adjusted by a given amount each unit of time. For example, each cycle of the input clock signal Fclk, the phase accumulator 306 of the DDS 300 increments by the value stored in the frequency register 302. If the frequency register 302 has an n-bit value Fsyn stored therein, the frequency of the generated output signal is equal to Fsyn*Fclk/(2**n).
The most significant m bits of the phase accumulator 306 are input to the cosine ROM 308, and the output of the cosine ROM 308 is input to the DAC 310 for output as an analog signal.
A conventional DDS, while generally equivalent in most applications to an oscillator, is nevertheless a digital, discrete-time, discrete-phase device.
FIG. 5A shows an exemplary output analog sinusoid having the desired frequency Fsyn (e.g., using an ideal DAC having infinite bandwidth and infinite resolution) superimposed on the actual resulting output of the discrete-time DDS 300. For simplicity of explanation, the discrete nature of the output signal shown in FIG. 5A is exaggerated.
FIG. 5B shows an exemplary resultant frequency spectrum of the discrete-time signal output from the DDS 300 shown in FIG. 4 based on the desired frequency output Fsyn shown in FIG. 5A. More particularly, FIG. 5B shows that, in addition to the desired tone at Fsyn, there are numerous alias components of the output signal at k*Fclk+/xe2x88x92 Fsyn.
For instance, note that in addition to the desired frequency output signal component 400, the output signal shown in FIG. 5B also includes alias components 402, 404 above and below one times the frequency of the input clock signal Fclk (components 402, and 404), alias components 406, 408 above and below two times the frequency of the input clock signal Fclk (components 406 and 408), alias components 410, 412 above and below three times the frequency of the input clock signal Fclk (components 410 and 412), etc.
As the desired output frequency Fsyn approaches one half the frequency of the input clock signal (i.e., Fclk/2) (designated by the arrow A), the Fclk-Fsyn alias also approaches Fclk/2 (designated by the arrow B), making the cutoff requirements of the anti-alias filter 312 that much more stringent, putting a practical upper limit on the usable output frequency of the DDS 300.
FIG. 6 shows a continuous-time square wave at the desired frequency Fsyn, and its discrete time equivalent as would be seen at the input to an otherwise conventional anti-alias filter. FIG. 7 shows an enlargement of the transitional region 302 shown in FIG. 6. Note from FIGS. 6 and 7 that the transitions are delayed until the next transition of the clock signal, which is the nature of a discrete time signal. These delays exacerbate the creation and propagation of alias components in the output signal.
As shown in FIG. 4, conventional removal of alias components, particularly those exacerbated and propagated by discretely timed circuits, requires the inclusion of a low pass filter 312, adding complexity, size and cost to conventional designs.
An alternative to the use of an anti-alias low pass filter is to increase the frequency of the input clock signal Fclk by at least several powers of two. However, while increasing the clock frequency does improve the time resolution to reduce or eliminate alias components, it does so at the disadvantage of increased power consumption proportional to the increase in clock frequency. In many applications, increased power consumption has other effects such as reduced operational time and thus decreased consumer demand.
There is thus a need for an improved apparatus and technique for eliminating alias signals without the need for a low pass filter and without increasing the frequency of the clock signal.
In accordance with the principles of the present invention, an interpolator having reduced alias signals in an output comprises a varying reference signal generator, a comparator, and a digital-to-analog converter. The comparator compares a level of an input signal to the varying reference signal generator, and causes the digital-to-analog converter to convert at a time when the input signal is at an equivalent level to the varying reference signal generator.
A method of removing an alias component in an output signal from a discretely timed circuit in accordance with another aspect of the present invention comprises prohibiting a transition in an output signal of the discretely timed circuit if a product of an output of a phase accumulator and a period value are greater than unity. A transition is allowed to occur in the output signal if the product is less than or equal to unity.
A method of removing an alias component in an output analog signal from a discretely timed circuit in accordance with yet another aspect of the present invention comprises intentionally moving a position of a transition in a digital signal in time in an interpolator, before conversion into an analog signal, based on a comparison of a desired signal to an input sample.
A method of removing low-order alias components from an output signal of a discretely timed circuit in accordance with still another aspect of the present invention comprises interpolating transitions within clock periods of a clock signal timing the discretely timed circuit, utilizing a period of the output signal and an instantaneous phase of the output signal, to improve a time resolution of the output signal.